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RISC-V ISA ManualUnprivileged Privileged Profiles Assembly SBI IOMMU Trace Server Platform CTR Debug AIA Server SoC RPMI RAS ERI

manual: bf7a196

Preface
1 Introduction
2 Base Instruction Sets
3 RISC-V Memory Models
4 Scalar Integer Extensions
5 Atomic Instructions
6 Scalar Floating-Point Extensions
7 Compressed Instructions
8 Bit Manipulation Extensions
9 Vector Extensions
10 Packed SIMD Extensions
11 Cryptography Extensions
12 Matrix Extensions
A RV32/64G Instruction Set Listings
B Memory Model Supplemental Material
C ISA Extension Naming Conventions
D RISC-V Assembly Code Examples
E Historical Rationale for Extensions

12 Matrix Extensions

12 Matrix Extensions

This chapter is a placeholder for forthcoming matrix extensions.

11 Cryptography Extensions

A RV32/64G Instruction Set Listings