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10 Parameters and Discovery

This document defines a number of parameters for describing aspects of the encoder such as the widths of buses, the presence or absence of optional features and the size of resources, as listed in Table 40 and Table 41.

Depending on the implementation, some parameters may be inherently fixed whilst others may be passed in to the design by some means.

Table 40. Parameters to the encoder - instruction trace

Parameter nameRangeDescription
arch_pThe architecture specification version with which the encoder is compliant (0 for initial version).
blocks_pNumber of times iretire, itype etc. are replicated
bpred_size_pNumber of entries in the branch predictor is 2bpred_size_p. Minimum number of entries is 2, so a value of 0 indicates that there is no branch predictor implemented.
cache_size_pNumber of entries in the jump target cache is 2cache_size_p. Minimum number of entries is 2, so a value of 0 indicates that there is no jump target cache implemented.
call_counter_size_pNumber of bits in the nested call counter is 2call_counter_size_p. Minimum number of entries is 2, so a value of 0 indicates that there is no implicit return call counter implemented.
ctype_width_pWidth of the ctype bus
context_width_pWidth of context bus
time_width_pWidth of time bus
ecause_width_pWidth of exception cause bus
ecause_choice_pNumber of bits of exception cause to match using multiple choice
f0s_width_pWidth of the subformat field in format 0 te_inst packets (see Section 7.8.1).
filter_context_p0 or 1Filtering on context supported when 1
filter_time_p0 or 1Filtering on time supported when 1
filter_excint_pFiltering on exception cause or interrupt supported when non_zero. Number of nested exceptions supported is 2filter_excint_p
filter_privilege_p0 or 1Filtering on privilege supported when 1
filter_tval_p0 or 1Filtering on trap value supported when 1 (provided filter_excint_p is non-zero)
iaddress_lsb_pLSB of instruction address bus to trace. 1 if compressed instructions are supported, 2 otherwise
iaddress_width_pWidth of instruction address bus. This is the same as DXLEN
iretire_width_pWidth of the iretire bus
ilastsize_width_pWidth of the ilastsize bus
itype_width_pWidth of the itype bus
nocontext_p0 or 1Exclude context from te_inst packets if 1
notime_p0 or 1Exclude time from te_inst packets if 1
privilege_width_pWidth of privilege bus
retires_pMaximum number of instructions that can be retired per block
return_stack_size_pNumber of entries in the return address stack is 2return_stack_size_p. Minimum number of entries is 2, so a value of 0 indicates that there is no implicit return stack implemented.
sijump_p0 or 1sijump is used to identify sequentially inferable jumps
impdef_width_pWidth of implementation-defined input bus

Table 41. Parameters to the encoder - data trace

Parameter nameRangeDescription
daddress_width_pWidth of the daddress bus
dblock_width_pWidth of the dblock bus
data_width_pWidth of the data bus
dsize_width_pWidth of the dsize bus
dtype_width_pWidth of the dtype bus
iaddr_lsbs_width_pWidth of the iaddr_lsbs bus
lrid_width_pWidth of the lrid bus
lresp_width_pWidth of the lresp bus
ldata_width_pWidth of the ldata bus
sdata_width_pWidth of the sdata bus

10.1 Discovery of encoder parameters

To operate correctly, the decoder must be able to determine some of the encoder’s parameters at runtime, in the form of discoverable attributes. These parameters must be discoverable by the decoder, or else be fixed at the default value (in other words, if an encoder does not make a particular parameter discoverable, it must implement only the default value of that parameter, which the decoder will also use). Table 42 lists the required discoverable attributes for instruction trace.

To access the discoverable attributes, some external entity, for example a debugger or a supervisory hart, must request it from the encoder. The encoder will provide the discovery information in one or more different formats. The preferred format is a packet which is sent over the trace infrastructure. Another format would be allowing the external entity to read the values from some register or memory mapped space maintained by the encoder. Section 10.2 gives an example of how this may be accomplished.

Table 42. Required instruction trace attributes

NameDefaultParameter mapping
arch0arch_p
bpred_size0bpred_size_p
cache_size0cache_size_p
call_counter_size0call_counter_size_p
context_width0context_width_p - 1
time_width0time_width_p - 1
ecause_width3ecause_width_p - 1
f0s_width0f0s_width_p
iaddress_lsb0iaddress_lsb_p - 1
iaddress_width31iaddress_width_p - 1
nocontext1nocontext
notime1notime
privilege_width1privilege_width_p - 1
return_stack_size0return_stack_size_p
sijump0sijump_p

For ease of use it is further recommended that all of the encoder’s parameters be mapped to discoverable attributes, even if not directly required by the decoder. In particular, attributes related to filtering capabilities. Table 43 lists the attributes associated with the filtering recommendations discussed in Section 5, Table 44 lists attributes related to other instruction trace parameters mentioned in this document, and Table 45 lists attributes related to data trace.

Table 43. Optional filtering attributes

NameDefaultParameter mapping
comparators0comparators_p - 1
filters0filters_p - 1
ecause_choice5ecause_choice_p
filter_context1filter_context_p
filter_time1filter_time_p
filter_excint1filter_excint_p
filter_privilege1filter_privilegep
filter_tval1filter_tval_p

Table 44. Other recommended attributes

NameDefaultDescription
ctype_width0ctype_width_p - 1
ilastsize_width0ilastsize_width_p - 1
itype_width3itype_width_p - 1
iretire_width1iretire_width_p - 1
retires0retires_p - 1
impdef_width0impdef_width_p - 1

Table 45. Data trace attributes

NameDefaultDescription
daddress_width31daddress_width_p - 1
dblock_width0dblock_width_p - 1
data_width31data_width_p - 1
dsize_width2dsize_width_p - 1
dtype_width0dtype_width_p - 1
iaddr_lsbs_width0iaddr_lsbs_width_p - 1
lrid_width0lrid_width_p - 1
lresp_width0lresp_width_p - 1
ldata_width31ldata_width_p - 1
sdata_width31sdata_width_p - 1

10.2 Example ipxact description

This section provides an example of discovery information represented in the ipxact form.

\<?xmlversion="1.0" encoding="UTF-8"?>
\<ipxact:component
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
\<ipxact:vendor>Siemens\</ipxact:vendor>
\<ipxact:library>TraceEncoder\</ipxact:library>
\<ipxact:name>TraceEncoder\</ipxact:name>
\<ipxact:version>0.8\</ipxact:version>
\<ipxact:memoryMaps>
\<ipxact:memoryMap>
\<ipxact:name>TraceEncoderRegisterMap\</ipxact:name>
\<ipxact:addressBlock>
\<ipxact:name>>TraceEncoderRegisterAddressBlock\</ipxact:name>
\<ipxact:baseAddress>0\</ipxact:baseAddress>
\<ipxact:range>128\</ipxact:range>
\<ipxact:width>64\</ipxact:width>

\<ipxact:register>
\<ipxact:name>discovery_info_0\</ipxact:name>
\<ipxact:addressOffset>'h0\</ipxact:addressOffset>
\<ipxact:size>64\</ipxact:size>
\<ipxact:access>read-only\</ipxact:access>
\<ipxact:field>
\<ipxact:name>version\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>0\</ipxact:bitOffset>
\<ipxact:bitWidth>4\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>minor_revision\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>4\</ipxact:bitOffset>
\<ipxact:bitWidth>4\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>arch\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>8\</ipxact:bitOffset>
\<ipxact:bitWidth>4\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>bpred_size\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>12\</ipxact:bitOffset>
\<ipxact:bitWidth>4\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>cache_size\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>16\</ipxact:bitOffset>
\<ipxact:bitWidth>4\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>call_counter_size\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>20\</ipxact:bitOffset>
\<ipxact:bitWidth>3\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>comparators\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>23\</ipxact:bitOffset>
\<ipxact:bitWidth>3\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>context_type_width\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>26\</ipxact:bitOffset>
\<ipxact:bitWidth>5\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>context_width\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>31\</ipxact:bitOffset>
\<ipxact:bitWidth>5\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>ecause_choice\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>36\</ipxact:bitOffset>
\<ipxact:bitWidth>3\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>ecause_width\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>39\</ipxact:bitOffset>
\<ipxact:bitWidth>4\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>filters\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>43\</ipxact:bitOffset>
\<ipxact:bitWidth>4\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>filter_context\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>47\</ipxact:bitOffset>
\<ipxact:bitWidth>1\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>filter_excint\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>48\</ipxact:bitOffset>
\<ipxact:bitWidth>4\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>filter_privilege\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>52\</ipxact:bitOffset>
\<ipxact:bitWidth>1\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>filter_tval\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>53\</ipxact:bitOffset>
\<ipxact:bitWidth>1\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>filter_impdef\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>54\</ipxact:bitOffset>
\<ipxact:bitWidth>1\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>f0s_width\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>55\</ipxact:bitOffset>
\<ipxact:bitWidth>2\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>iaddress_lsb\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>57\</ipxact:bitOffset>
\<ipxact:bitWidth>2\</ipxact:bitWidth>
\</ipxact:field>
\</ipxact:register>

\<ipxact:register>
\<ipxact:name>discovery_info_1\</ipxact:name>
\<ipxact:addressOffset>'h4\</ipxact:addressOffset>
\<ipxact:size>64\</ipxact:size>
\<ipxact:access>read-only\</ipxact:access>
\<ipxact:field>
\<ipxact:name>iaddress_width\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>0\</ipxact:bitOffset>
\<ipxact:bitWidth>7\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>ilastsize_width\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>7\</ipxact:bitOffset>
\<ipxact:bitWidth>7\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>itype_width\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>14\</ipxact:bitOffset>
\<ipxact:bitWidth>7\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>iretire_width\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>21\</ipxact:bitOffset>
\<ipxact:bitWidth>7\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>nocontext\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>28\</ipxact:bitOffset>
\<ipxact:bitWidth>1\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>privilege_width\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>29\</ipxact:bitOffset>
\<ipxact:bitWidth>2\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>retires\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>31\</ipxact:bitOffset>
\<ipxact:bitWidth>3\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>return_stack_size\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>34\</ipxact:bitOffset>
\<ipxact:bitWidth>4\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>sijump\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>38\</ipxact:bitOffset>
\<ipxact:bitWidth>1\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>taken_branches\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>39\</ipxact:bitOffset>
\<ipxact:bitWidth>4\</ipxact:bitWidth>
\</ipxact:field>
\<ipxact:field>
\<ipxact:name>impdef_width\</ipxact:name>
\<ipxact:description>text\</ipxact:description>
\<ipxact:bitOffset>43\</ipxact:bitOffset>
\<ipxact:bitWidth>5\</ipxact:bitWidth>
\</ipxact:field>
\</ipxact:register>

\</ipxact:addressBlock>
\<ipxact:addressUnitBits>8\</ipxact:addressUnitBits>
\</ipxact:memoryMap>
\</ipxact:memoryMaps>
\</ipxact:component>