Skip to main content

6 RVB23 Profiles

This chapter specifies the RVB23 profile family. RVB23 is the first major release of the RVB series of RISC-V Application Processor Profile.

RVB profiles are intended to be used for customized 64-bit application processors that will run rich OS stacks, but usually as a custom build of standard OS source-code distributions. The approach is to provide a large guaranteed set of relatively inexpensive and/or widely beneficial features but allow optionality for more expensive and/or more targeted extensions.

Unlike the RVA profiles, it is explicitly a non-goal of RVB profiles to provide a single standard ISA interface supporting a wide variety of binary kernel and binary application software distributions. However, individual software ecosystems may build upon RVB profiles to produce a more targeted standard interface for a certain market.

Only user-mode (RVB23U64) and supervisor-mode (RVB23S64) profiles are specified in this family.

6.1 RVB23U64 Profile​

The RVB23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit RVB applications processors.

6.1.1 RVB23U64 Mandatory Base​

RV64I is the mandatory base ISA for RVB23U64 and is little-endian. As per the unprivileged architecture specification, the ECALL instruction causes a requested trap to the execution environment.

6.1.2 RVB23U64 Mandatory Extensions​

The following mandatory extensions in RVB23U64 were also mandatory in RVA22U64.

  • M Integer multiplication and division.
  • A Atomic instructions.
  • F Single-precision floating-point instructions.
  • D Double-precision floating-point instructions.
  • C Compressed instructions.
  • B Bit-manipulation instructions.
  • Zicsr CSR instructions. These are implied by presence of F.
  • Zicntr Base counters and timers.
  • Zihpm Hardware performance counters.
  • Ziccif Main memory regions with both the coherence and cacheability PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVB23) are atomic.
  • Ziccrse Main memory regions with both the coherence and cacheability PMAs must support RsrvEventual.
  • Ziccamoa Main memory regions with both the coherence and cacheability PMAs must support AMOArithmetic.
  • Zicclsm Misaligned loads and stores to main memory regions with both the coherence and cacheability PMAs must be supported.
  • Za64rs Reservation sets must be contiguous, naturally aligned, and a maximum of 64 bytes.
  • Zihintpause Pause hint.
  • Zic64b Cache blocks must be 64 bytes in size, naturally aligned in the address space.
  • Zicbom Cache-Block Management Operations.
  • Zicbop Cache-Block Prefetch Operations.
  • Zicboz Cache-Block Zero Operations.
  • Zkt Data-independent execution latency.

The following mandatory extensions are also present in RVA23U64:

  • Zihintntl Non-temporal locality hints.
  • Zicond Integer conditional operations.
  • Zimop May-be-operations.
  • Zcmop Compressed may-be-operations.
  • Zcb Additional compressed instructions.
  • Zfa Additional floating-point instructions.
  • Zawrs Wait-on-reservation-set instructions.

6.1.3 RVB23U64 Optional Extensions​

RVB23U64 has 18 profile options listed below.

6.1.3.1 Localized Options​

The following extensions are localized options in both RVA23U64 and RVB23U64:

  • Zvkng Vector crypto NIST Algorithms with GCM.
  • Zvksg Vector crypto ShangMi Algorithms with GCM.

The following extensions options are localized options in RVB23U64 but are not present in RVA23U64:

  • Zvkg Vector GCM/GMAC instructions.
  • Zvknc Vector crypto NIST algorithms with carryless multiply.
  • Zvksc Vector crypto ShangMi algorithms with carryless multiply.
note

RVA profiles mandate the higher-performing but more expensive GHASH options when adding vector crypto. To reduce implementation cost, RVB profiles also allow these carryless multiply options (Zvknc and Zvksc) to implement GCM efficiently, with GHASH available as a separate option.

  • Zkn Scalar crypto NIST algorithms.
  • Zks Scalar crypto ShangMi algorithms.
note

RVA23 profiles drop support for scalar crypto as an option, as the vector extension is now mandatory in RVA23. RVB23 profiles support scalar crypto, as the vector extension is optional in RVB23.

6.1.3.2 Development Options​

The following are new development options intended to become mandatory in a later RVB profile:

  • Zabha Byte and halfword atomic memory operations.
  • Zacas Compare-and-swap instructions.
  • Ziccamoc Main memory regions with both the coherence and cacheability PMAs must provide AMOCASQ-level PMA support.
  • Zama16b Misaligned loads, stores and AMOs to main memory regions with both the coherence and cacheability PMAs that do not cross a naturally aligned 16-byte boundary are atomic.

6.1.3.3 Expansion Options​

The following are expansion options in RVB23U64, but are mandatory in RVA23U64.

  • Zfhmin Scalar half-precision floating-point transfer and convert.
  • V Vector extension.
note

Unclear if other Zve* extensions should also be supported in RVB.

  • Zvfhmin Vector minimal half-precision floating-point.
  • Zvbb Vector basic bit-manipulation instructions.
  • Zvkt Vector data-independent execution latency.
  • Supm Pointer masking, with the execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

The following extensions are expansion options in both RVA23U64 and RVB23U64:

  • Zfh Scalar half-precision floating-point.
  • Zbc Scalar carryless multiplication.
  • Zicfilp Landing Pads.
  • Zicfiss Shadow Stack.
  • Zvfh Vector half-precision floating-point.
  • Zfbfmin Scalar BF16 converts.
  • Zvfbfmin Vector BF16 converts.
  • Zvfbfwma Vector BF16 widening mul-add.

The following are expansion options for RVB23U64 as they are not intended to be made mandatory in future RVB profiles, but are listed as RVA23U64 development options as they are intended to become mandatory in future RVA profiles.

  • Zvbc Vector carryless multiplication.

6.1.3.4 Transitory Options​

There are no transitory options in RVB23U64.

6.1.4 RVB23U64 Recommendations​

Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.

6.2 RVB23S64 Profile​

The RVB23S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVB23S64 is based on privileged architecture version 1.13.

6.2.1 RVB23S64 Mandatory Base​

RV64I is the mandatory base ISA for RVB23S64 and is little-endian. The ECALL instruction operates as per the unprivileged architecture specification. An ECALL in user mode causes a contained trap to supervisor mode. An ECALL in supervisor mode causes a requested trap to the execution environment.

6.2.2 RVB23S64 Mandatory Extensions​

The following unprivileged extensions are mandatory:

  • The RVB23S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVB23U64.
  • Zifencei Instruction-fetch fence.
note

Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVB23 application processors. A new instruction-cache coherence mechanism, Ziccid, might be added as an option in the future.

The following privileged extensions are mandatory, and are also mandatory in RVA23S64.

  • Ss1p13 Supervisor architecture version 1.13.
note

Ss1p13 supersedes Ss1p12.

  • Svnapot NAPOT translation contiguity.
note

Svnapot is very low cost to provide, so is made mandatory even in RVB.

  • Svbare The satp mode Bare must be supported.
  • Sv39 Page-Based 39-bit Virtual-Memory System.
  • Svade Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.
  • Ssccptr Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.
  • Sstvecd stvec.MODE must be capable of holding the value 0 (Direct). When stvec.MODE=Direct, stvec.BASE must be capable of holding any valid four-byte-aligned address.
  • Sstvala stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions that are defined to write an address to stval, other than those caused by execution of the EBREAK or C.EBREAK instructions. For virtual-instruction and illegal-instruction exceptions, stval must be written with the faulting instruction.
  • Sscounterenw For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable.
  • Svpbmt Page-based memory types.
  • Svinval Fine-grained address-translation cache invalidation.
  • Sstc supervisor-mode timer interrupts.
  • Sscofpmf Count overflow and mode-based filtering.
  • Ssu64xl sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).

6.2.3 RVB23S64 Optional Extensions​

RVB23S64 has the same unprivileged options as RVB23U64.

The privileged options in RVB23S64 are listed in the following sections.

6.2.3.1 Localized Options​

There are no privileged localized options in RVB23S64.

6.2.3.2 Development Options​

There are no privileged development options in RVB23S64.

6.2.3.3 Expansion Options​

The following are privileged expansion options in RVB23S64, but are mandatory in RVA23S64:

  • Ssnpm Pointer masking, with senvcfg.PMM supporting at minimum, settings PMLEN=0 and PMLEN=7.
  • Sha The augmented hypervisor extension.

When the hypervisor extension is implemented, the following are also mandatory:

  • If the hypervisor extension is implemented and pointer masking (Ssnpm) is supported then henvcfg.PMM must support at minimum, settings PMLEN=0 and PMLEN=7.

The following are privileged expansion options in RVB23S64 that are also privileged expansion options in RVA23S64:

  • Sv48 Page-based 48-bit virtual-memory system.
  • Sv57 Page-based 57-bit virtual-memory system.
  • Svadu Hardware A/D bit updates.
  • Zkr Entropy CSR.
  • Sdtrig Debug triggers.
  • Ssstrict No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.
note

Ssstrict does not prescribe behavior for the custom encoding spaces or CSRs.

note

Ssstrict definition applies to the execution environment claiming to be RVB23S64-compatible. That execution environment will take a contained trap to supervisor-mode (however that trap is implemented, including, but not limited to, emulation/delegation in the outer execution environment). Ssstrict (and all the other RVB23S64 mandates and options) does not apply to any guest VMs run by a hypervisor. An RVB23S64 hypervisor can provide guest VMs that are also RVB23S64-compatible but with an expanded set of emulated standard instructions. An RVB23S64 hypervisor can also choose to implement guest VMs that are not RVB23S64 compatible (e.g., only RVA20S64).

  • Svvptc Transitions from invalid to valid PTEs will be visible in bounded time without an explicit memory-management fence.
  • Sspm Supervisor-mode pointer masking, with the supervisor execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

6.2.4 RVB23S64 Recommendations​

  • Implementations are strongly recommended to raise illegal-instruction exceptions when attempting to execute unimplemented opcodes.