Skip to main content

5 RVA23 Profiles

The RVA23 profiles are intended to align implementations of RISC-V 64-bit application processors to allow binary software ecosystems to rely on a large set of guaranteed extensions and a small number of discoverable coarse-grain options. It is explicitly a non-goal of RVA23 to allow more hardware implementation flexibility by supporting only a minimal set of features and a large number of fine-grain extensions.

Only user-mode (RVA23U64) and supervisor-mode (RVA23S64) profiles are specified in this family.

5.1 RVA23U64 Profile​

The RVA23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors. This is the most important profile within the application processor family in terms of the amount of software that targets this profile.

5.1.1 RVA23U64 Mandatory Base​

RV64I is the mandatory base ISA for RVA23U64 and is little-endian. As per the unprivileged architecture specification, the ECALL instruction causes a requested trap to the execution environment.

5.1.2 RVA23U64 Mandatory Extensions​

The following mandatory extensions were present in RVA22U64.

  • M Integer multiplication and division.
  • A Atomic instructions.
  • F Single-precision floating-point instructions.
  • D Double-precision floating-point instructions.
  • C Compressed instructions.
  • B Bit-manipulation instructions.
  • Zicsr CSR instructions. These are implied by presence of F.
  • Zicntr Base counters and timers.
  • Zihpm Hardware performance counters.
  • Ziccif Main memory regions with both the coherence and cacheability PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVA23) are atomic.
  • Ziccrse Main memory regions with both the coherence and cacheability PMAs must support RsrvEventual.
  • Ziccamoa Main memory regions with both the coherence and cacheability PMAs must support AMOArithmetic.
  • Zicclsm Misaligned loads and stores to main memory regions with both the coherence and cacheability PMAs must be supported.
  • Za64rs Reservation sets must be contiguous, naturally aligned, and a maximum of 64 bytes.
  • Zihintpause Pause hint.
  • Zic64b Cache blocks must be 64 bytes in size, naturally aligned in the address space.
  • Zicbom Cache-Block Management Operations.
  • Zicbop Cache-Block Prefetch Operations.
  • Zicboz Cache-Block Zero Operations.
  • Zfhmin Scalar half-precision floating-point transfer and convert.
  • Zkt Data-independent execution latency.

The following mandatory extensions are new in RVA23U64:

  • V Vector extension.
note

V was optional in RVA22U64.

  • Zvfhmin Vector minimal half-precision floating-point.
  • Zvbb Vector basic bit-manipulation instructions.
  • Zvkt Vector data-independent execution latency.
  • Zihintntl Non-temporal locality hints.
  • Zicond Integer conditional operations.
  • Zimop may-be-operations.
  • Zcmop Compressed may-be-operations.
  • Zcb Additional compressed instructions.
  • Zfa Additional floating-point instructions.
  • Zawrs Wait-on-reservation-set instructions.
  • Supm Pointer masking, with the execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

5.1.3 RVA23U64 Optional Extensions​

5.1.3.1 Localized Options​

The following localized options are new in RVA23U64:

  • Zvkng Vector crypto NIST algorithms with GCM.
  • Zvksg Vector crypto ShangMi algorithms with GCM.
note

The scalar crypto extensions Zkn and Zks that were options in RVA22 are not options in RVA23. The goal is for both hardware and software vendors to move to use vector crypto, as vectors are now mandatory and vector crypto is substantially faster than scalar crypto.

note

We have included only the Zvkng/Zvksg options with GCM to standardize on a higher performance crypto alternative. Zvbc is listed as a development option for use in other algorithms, and will become mandatory. Scalar Zbc is now listed as an expansion option, i.e., it will probably not become mandatory.

5.1.3.2 Development Options​

The following are new development options intended to become mandatory in a future RVA profile.

  • Zabha Byte and halfword atomic memory operations.
  • Zacas Compare-and-swap instructions.
  • Ziccamoc Main memory regions with both the coherence and cacheability PMAs must provide AMOCASQ-level PMA support.
note

Ziccamoc ensures compare-and-swap instructions are properly supported in main memory regions.

  • Zvbc Vector carryless multiplication.
  • Zama16b Misaligned loads, stores and AMOs to main memory regions with both the coherence and cacheability PMAs that do not cross a naturally aligned 16-byte boundary are atomic.
note

Zama16b represents the presence of the new Misaligned Atomicity Granule feature added in Sm1p13.

5.1.3.3 Expansion Options​

The following expansion options were also present in RVA22U64:

  • Zfh Scalar half-precision floating-point.

The following are new expansion options in RVA23U64:

5.1.3.4 Transitory Options​

There are no transitory options in RVA23U64.

note

Scalar crypto is no longer an option in RVA23U64, though the Zbc extension has now been exposed as an expansion option.

5.1.4 RVA23U64 Recommendations​

Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.

5.2 RVA23S64 Profile​

The RVA23S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA23S64 is based on privileged architecture version 1.13.

5.2.1 RVA23S64 Mandatory Base​

RV64I is the mandatory base ISA for RVA23S64 and is little-endian. The ECALL instruction operates as per the unprivileged architecture specification. An ECALL in user mode causes a contained trap to supervisor mode. An ECALL in supervisor mode causes a requested trap to the execution environment.

5.2.2 RVA23S64 Mandatory Extensions​

The following unprivileged extensions are mandatory:

  • The RVA23S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVA23U64.
  • Zifencei Instruction-fetch fence.
note

Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVA23 application processors. A new instruction-cache coherence mechanism, Ziccid, might be added as an option in the future.

The following privileged extensions are mandatory:

  • Ss1p13 Supervisor architecture version 1.13.
note

Ss1p13 supersedes Ss1p12.

The following privileged extensions were also mandatory in RVA22S64:

  • Svbare The satp mode Bare must be supported.
  • Sv39 Page-based 39-bit virtual-Memory system.
  • Svade Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.
  • Ssccptr Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.
  • Sstvecd stvec.MODE must be capable of holding the value 0 (Direct). When stvec.MODE=Direct, stvec.BASE must be capable of holding any valid four-byte-aligned address.
  • Sstvala stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions that are defined to write an address to stval, other than those caused by execution of the EBREAK or C.EBREAK instructions. For virtual-instruction and illegal-instruction exceptions, stval must be written with the faulting instruction.
  • Sscounterenw For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable.
  • Svpbmt Page-based memory types
  • Svinval Fine-grained address-translation cache invalidation.

The following are new mandatory extensions:

  • Svnapot NAPOT translation contiguity.
note

Svnapot was optional in RVA22.

  • Sstc supervisor-mode timer interrupts.
note

Sstc was optional in RVA22.

  • Sscofpmf count overflow and mode-based filtering.
  • Ssnpm Pointer masking, with senvcfg.PMM and henvcfg.PMM supporting, at minimum, settings PMLEN=0 and PMLEN=7.
  • Ssu64xl sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).
note

Ssu64xl was optional in RVA22.

  • Sha The augmented hypervisor extension.
note

Sha was optional in RVA22.

5.2.3 RVA23S64 Optional Extensions​

RVA23S64 has the same unprivileged options as RVA23U64.

The privileged options in RVA23S64 are listed in the following sections.

5.2.3.1 Localized Options​

There are no privileged localized options in RVA23S64.

5.2.3.2 Development Options​

There are no privileged development options in RVA23S64.

5.2.3.3 Expansion Options​

The following privileged expansion options were present in RVA22S64:

  • Sv48 Page-based 48-bit virtual-memory system.
  • Sv57 Page-based 57-bit virtual-memory system.
  • Zkr Entropy CSR.

The following are new privileged expansion options in RVA23S64

  • Svadu Hardware A/D bit updates.
  • Sdtrig Debug triggers.
  • Ssstrict No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.
note

Ssstrict does not prescribe behavior for the custom encoding spaces or CSRs.

note

Ssstrict definition applies to the execution environment claiming to be RVA23S64-compatible, which must have the hypervisor extension. That execution environment will take a contained trap to supervisor-mode (however that trap is implemented, including, but not limited to, emulation/delegation in the outer execution environment). Ssstrict (and all the other RVA23S64 mandates and options) does not apply to any guest VMs run by a hypervisor. An RVA23S64 hypervisor can provide guest VMs that are also RVA23S64-compatible but with an expanded set of emulated standard instructions. An RVA23S64 hypervisor can also choose to implement guest VMs that are not RVA23S64 compatible (e.g., lacking H, or only RVA20S64).

  • Svvptc Transitions from invalid to valid PTEs will be visible in bounded time without an explicit memory-management fence.
  • Sspm Supervisor-mode pointer masking, with the supervisor execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

5.2.3.4 Transitory Options​

There are no privileged transitory options in RVA23S64.

5.2.4 RVA23S64 Recommendations​

  • Implementations are strongly recommended to raise illegal-instruction exceptions when attempting to execute unimplemented opcodes or access unimplemented CSRs.