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4 RVA22 Profiles

The RVA22 profiles are intended to be used for 64-bit application processors running rich OS stacks. Only user-mode (RVA22U64) and supervisor-mode (RVA22S64) profiles are specified in this family.

4.1 RVA22U64 Profile​

The RVA22U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors. This is the most important profile within the application processor family in terms of the amount of software that targets this profile.

4.1.1 RVA22U64 Mandatory Base​

RV64I is the mandatory base ISA for RVA22U64 and is little-endian.

As per the unprivileged architecture specification, the ecall instruction causes a requested trap to the execution environment.

4.1.2 RVA22U64 Mandatory Extensions​

The following mandatory extensions were present in RVA20U64.

  • M Integer multiplication and division.
  • A Atomic instructions.
  • F Single-precision floating-point instructions.
  • D Double-precision floating-point instructions.
  • C Compressed Instructions.
  • Zicsr CSR instructions. These are implied by presence of F.
  • Zicntr Base counters and timers.
  • Ziccif Main memory regions with both the coherence and cacheability PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVA22) are atomic.
  • Ziccrse Main memory regions with both the coherence and cacheability PMAs must support RsrvEventual.
  • Ziccamoa Main memory regions with both the coherence and cacheability PMAs must support AMOArithmetic.
  • Zicclsm Misaligned loads and stores to main memory regions with both the coherence and cacheability PMAs must be supported.
note

Even though mandated, misaligned loads and stores might execute extremely slowly. Standard software distributions should assume their existence only for correctness, not for performance.

The following mandatory feature was further restricted in RVA22U64:

  • Za64rs Reservation sets must be contiguous, naturally aligned, and a maximum of 64 bytes.
note

The maximum reservation size has been reduced to match the required cache block size. The minimum reservation size is effectively set by the instructions in the mandatory Zalrsc extension.

The following mandatory extensions are new for RVA22U64.

  • B Bit-manipulation instructions.
  • Zihpm Hardware performance counters.
note

Zihpm was optional in RVA20U64.

note

While the PAUSE instruction is a HINT can be implemented as a NOP and hence trivially supported by hardware implementers, its inclusion in the mandatory extension list signifies that software should use the instruction whenever it would make sense and that implementors are expected to exploit this information to optimize hardware execution.

  • Zic64b Cache blocks must be 64 bytes in size, naturally aligned in the address space.
note

While the general RISC-V specifications are agnostic to cache block size, selecting a common cache block size simplifies the specification and use of the following cache-block extensions within the application processor profile. Software does not have to query a discovery mechanism and/or provide dynamic dispatch to the appropriate code. We choose 64 bytes at it is effectively an industry standard. Implementations may use longer cache blocks to reduce tag cost provided they use 64-byte sub-blocks to remain compatible. Implementations may use shorter cache blocks provided they sequence cache operations across the multiple cache blocks comprising a 64-byte block to remain compatible.

  • Zicbom Cache-Block Management Operations.
  • Zicbop Cache-Block Prefetch Operations.
note

As with other HINTS, the inclusion of prefetches in the mandatory set of extensions indicates that software should generate these instructions where they are expected to be useful, and hardware is expected to exploit that information.

  • Zicboz Cache-Block Zero Operations.
  • Zfhmin Scalar half-precision floating-point transfer and convert.
note

The hardware cost for Zfhmin is low, and mandating it avoids adding an option to the profile.

  • Zkt Data-independent execution time.
note

Mandating Zkt enables portable libraries for safe basic cryptographic operations. It is expected that application processors will naturally have this property and so implementation cost is low, if not zero, in most systems that would support RVA22.

4.1.3 RVA22U64 Optional Extensions​

RVA22U64 has four profile options (Zfh, V, Zkn, Zks):

  • Zfh Scalar half-precision floating-point.
note

A future profile might mandate Zfh.

  • V Vector Extension.
note

The smaller vector extensions (Zve32f, Zve32x, Zve64d, Zve64f, Zve64x) are not provided as separately supported profile options. The full V extension is specified as the only supported profile option.

  • Zkn Scalar Crypto NIST Algorithms.
  • Zks Scalar Crypto ShangMi Algorithms.
note

The smaller component scalar crypto extensions (Zbc, Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh) are not provided as separate options in the profile. Profile implementers should provide all of the instructions in a given algorithm suite as part of the Zkn or Zks supported options.

note

Access to the entropy source (Zkr) in a system is usually carefully controlled. While the design supports unprivileged access to the entropy source, this is unlikely to be commonly used in an application processor, and so Zkr was not added as a profile option. This also means the roll-up Zk was not added as a profile option.

note

The Zfinx, Zdinx, Zhinx, Zhinxmin extensions are incompatible with the profile mandates to support the F and D extensions.

4.1.4 RVA22U64 Recommendations​

Recommendations are not strictly mandated but are included to guide implementers making design choices.

Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.

4.2 RVA22S64 Profile​

The RVA22S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA22S64 is based on privileged architecture version 1.12.

4.2.1 RVA22S64 Mandatory Base​

RV64I is the mandatory base ISA for RVA22S64 and is little-endian.

The ecall instruction operates as per the unprivileged architecture specification. An ecall in user mode causes a contained trap to supervisor mode. An ecall in supervisor mode causes a requested trap to the execution environment.

4.2.2 RVA22S64 Mandatory Extensions​

The following unprivileged extensions are mandatory:

  • The RVA22S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVA22U64.
  • Zifencei Instruction-fetch fence.
note

Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVA22 application processors. A new instruction-cache coherence mechanism is under development which might be added as an option in the future.

The following privileged extensions are mandatory:

  • Ss1p12 Privileged Architecture version 1.12.
note

Ss1p12 supersedes Ss1p11.

  • Svbare The satp mode Bare must be supported.
  • Sv39 Page-Based 39-bit Virtual-Memory System.
  • Svade Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.
  • Ssccptr Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.
  • Sstvecd stvec.MODE must be capable of holding the value 0 (Direct). When stvec.MODE=Direct, stvec.BASE must be capable of holding any valid four-byte-aligned address.
  • Sstvala stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions other than those caused by execution of the EBREAK or C.EBREAK instructions. For virtual-instruction and illegal-instruction exceptions, stval must be written with the faulting instruction.
  • Sscounterenw For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable.
  • Svpbmt Page-Based Memory Types
  • Svinval Fine-Grained Address-Translation Cache Invalidation

4.2.3 RVA22S64 Optional Extensions​

RVA22S64 has four unprivileged options (Zfh, V, Zkn, Zks) from RVA22U64, and eight privileged options (Sv48, Sv57, Svnapot, Ssu64xl, Sstc, Sscofpmf, Zkr, H).

The privileged optional extensions are:

  • Sv48 Page-Based 48-bit Virtual-Memory System.
  • Sv57 Page-Based 57-bit Virtual-Memory System.
  • Svnapot NAPOT Translation Contiguity
  • Ssu64xl sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).
  • Sstc supervisor-mode timer interrupts.
note

Sstc was not made mandatory in RVA22S64 as it is a more disruptive change affecting system-level architecture, and will take longer for implementations to adopt.

  • Sscofpmf Count Overflow and Mode-Based Filtering.
note

Platforms may choose to mandate the presence of Sscofpmf.

  • Zkr Entropy CSR.
note

Technically, Zk is also a privileged-mode option capturing that Zkr, Zkn, and Zkt are all implemented. However, the Zk rollup is less descriptive than specifying the individual extensions explicitly.

  • Sha The augmented hypervisor extension.

4.2.4 RVA22S64 Recommendations​

  • Implementations are strongly recommended to raise illegal-instruction exceptions when attempting to execute unimplemented opcodes.