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3 RVA20 Profiles

The RVA20 profiles are intended to be used for 64-bit application processors running rich OS stacks. Only user-mode (RVA20U64) and supervisor-mode (RVA20S64) profiles are specified in this family.

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There is no machine-mode profile currently defined for application processor families. A machine-mode profile for application processors would only be used in specifying platforms for portable machine-mode software. Given the relatively low volume of portable M-mode software in this domain, the wide variety of potential M-mode code, and the very specific needs of each type of M-mode software, we are not specifying individual M-mode ISA requirements in the A-family profiles.

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Only XLEN=64 application processor profiles are currently defined. It would be possible to also define very similar XLEN=32 variants.

3.1 RVA20U64 Profile​

The RVA20U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors. This is the most important profile within the application processor family in terms of the amount of software that targets this profile.

RVA20U64 has one optional extension (Zihpm).

3.1.1 RVA20U64 Mandatory Base​

RV64I is the mandatory base ISA for RVA20U64, and is little-endian.

As per the unprivileged architecture specification, the ecall instruction causes a requested trap to the execution environment.

The fence.tso instruction is mandatory.

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The fence.tso instruction was incorrectly described as optional in the 2019 ratified specifications. Later versions of the specification of FENCE.TSO correctly indicate that the instruction is mandatory.

3.1.2 RVA20U64 Mandatory Extensions​

  • M Integer multiplication and division.
  • A Atomic instructions.
  • F Single-precision floating-point instructions.
  • D Double-precision floating-point instructions.
  • C Compressed Instructions.
  • Zicsr CSR instructions. These are implied by presence of Zicntr or F.
  • Zicntr Base counters and timers.
  • Ziccif Main memory regions with both the coherence and cacheability PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVA20) are atomic.
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The fetch atomicity requirement facilitates runtime patching of aligned instructions.

  • Ziccrse Main memory regions with both the coherence and cacheability PMAs must support RsrvEventual.
  • Ziccamoa Main memory regions with both the coherence and cacheability PMAs must support AMOArithmetic.
  • Za128rs Reservation sets must be contiguous, naturally aligned, and at most 128 bytes in size.
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The minimum reservation set size is effectively determined by the size of atomic accesses in the Zalrsc extension.

  • Zicclsm Misaligned loads and stores to main memory regions with both the coherence and cacheability PMAs must be supported.
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This requires misaligned support for all regular load and store instructions (including scalar and vector) but not AMOs or other specialized forms of memory access. Even though mandated, misaligned loads and stores might execute extremely slowly. Standard software distributions should assume their existence only for correctness, not for performance.

3.1.3 RVA20U64 Optional Extensions​

  • Zihpm Hardware performance counters.
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Hardware performance counters are a supported option in RVA20. The number of counters is platform-specific.

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The rationale to not make Q an optional extension is that quad-precision floating-point is unlikely to be implemented in hardware, and so we do not require or expect A-profile software to expend effort optimizing use of Q instructions in case they are present.

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Zifencei is not classed as a supported option in the user-mode profile because it is not sufficient by itself to produce the desired effect in a multiprogrammed multiprocessor environment without OS support, and so the instruction cache flush should always be performed using an OS call rather than using the fence.i instruction. fence.i semantics can be expensive to implement for some hardware memory hierarchy designs, and so alternative non-standard instruction-cache coherence mechanisms can be used behind the OS abstraction. A separate extension is being developed for more general and efficient instruction cache coherence.

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The execution environment must provide a means to synchronize writes to instruction memory with instruction fetches, the implementation of which likely relies on the Zifencei extension. For example, RISC-V Linux supplies the __riscv_flush_icache system call and a corresponding vDSO call.

3.1.4 RVA20U64 Recommendations​

Recommendations are not strictly mandated but are included to guide implementers making design choices.

Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.

3.2 RVA20S64 Profile​

The RVA20S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA20S64 is based on privileged architecture version 1.11.

RVA20S64 has one unprivileged option (Zihpm) and one privileged option (Sv48).

3.2.1 RVA20S64 Mandatory Base​

RV64I is the mandatory base ISA for RVA20S64, and is little-endian.

The ecall instruction operates as per the unprivileged architecture specification. An ecall in user mode causes a contained trap to supervisor mode. An ecall in supervisor mode causes a requested trap to the execution environment.

3.2.2 RVA20S64 Mandatory Extensions​

The following unprivileged extensions are mandatory:

  • The RVA20S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVA20U64.
  • Zifencei Instruction-fetch fence.
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Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVA20 application processors. A new instruction-cache coherence mechanism is under development which might be added as an option in the future.

The following privileged extensions are mandatory:

  • Ss1p11 Privileged Architecture version 1.11.
  • Svbare The satp mode Bare must be supported.
  • Sv39 Page-Based 39-bit Virtual-Memory System.
  • Svade Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.
  • Ssccptr Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.
  • Sstvecd stvec.MODE must be capable of holding the value 0 (Direct). When stvec.MODE=Direct, stvec.BASE must be capable of holding any valid four-byte-aligned address.
  • Sstvala stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions that are defined to write an address to stval, other than those caused by execution of the EBREAK or C.EBREAK instructions. For virtual-instruction and illegal-instruction exceptions, stval must be written with the faulting instruction.

3.2.3 RVA20S64 Optional Extensions​

RVA20S64 has one unprivileged option.

  • Zihpm Hardware performance counters.
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The number of counters is platform-specific.

RVA20S64 has the following privileged options:

  • Sv48 Page-Based 48-bit Virtual-Memory System.
  • Ssu64xl sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).