9 "Sh" Hypervisor Extensions
This chapter is currently being restructured. Its contents are normative, but the presentation might appear disjoint.
9.1 Shvstvecd Extension for Direct Trap Vectoring, Version 1.0
If the Shvstvecd extension is implemented, then vstvec.MODE must be capable
of holding the value 0 (Direct).
Furthermore, when vstvec.MODE=Direct, vstvec.BASE must be capable of
holding any valid four-byte-aligned address.
9.2 Shcounterenw Extension for Counter-Enable Writability, Version 1.0
If the Shcounterenw extension is implemented, then for any hpmcounter that
is not read-only zero, the corresponding bit in hcounteren must be writable.
9.3 Shvstvala Extension for Trap Value Reporting, Version 1.0
If the Shvstvala extension is implemented, vstval must be written in all
cases described in sstvala for stval.
9.4 Shtvala Extension for Trap Value Reporting, Version 1.0
If the Shtvala extension is implemented, htval must be written with the
faulting guest physical address in all circumstances permitted by the ISA.
9.5 Shvsatpa Extension for Translation Mode Support, Version 1.0
If the Shvsatpa extension is implemented, all translation modes supported in
satp must be supported in vsatp.
9.6 Shgatpa Extension for Translation Mode Support, Version 1.0
If the Shgatpa extension is implemented, then for each supported virtual
memory scheme Sv_NN_ supported in satp, the corresponding hgatp Sv_NN_x4
mode must be supported.
Furthermore, the hgatp mode Bare must also be supported.
9.7 Sha Augmented Hypervisor Extension
The Augmented Hypervisor Extension, Sha, adds several minor features to the hypervisor extension. It depends on the following extensions: