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2 Control and Status Registers (CSRs)

The SYSTEM major opcode is used to encode all privileged instructions in the RISC-V ISA. These can be divided into two main classes: those that atomically read-modify-write control and status registers (CSRs), which are defined in the Zicsr extension, and all other privileged instructions. The privileged architecture requires the Zicsr extension; which other privileged instructions are required depends on the privileged-architecture feature set.

In addition to the unprivileged state described in Volume I of this manual, an implementation may contain additional CSRs, accessible by some subset of the privilege levels using the CSR instructions described in Zicsr. In this chapter, we map out the CSR address space. The following chapters describe the function of each of the CSRs according to privilege level, as well as the other privileged instructions which are generally closely associated with a particular privilege level. Note that although CSRs and instructions are associated with one privilege level, they are also accessible at all higher privilege levels.

Standard CSRs do not have side effects on reads but may have side effects on writes.

2.1 CSR Address Mapping Conventions​

The standard RISC-V ISA sets aside a 12-bit encoding space (csr[11:0]) for up to 4,096 CSRs. By convention, the upper 4 bits of the CSR address (csr[11:8]) are used to encode the read and write accessibility of the CSRs according to privilege level as shown in Table 3. The top two bits (csr[11:10]) indicate whether the register is read/write (00,01, or 10) or read-only (11). The next two bits (csr[9:8]) encode the lowest privilege level that can access the CSR, with the pattern 10 representing hypervisor CSRs.

note

The CSR address convention uses the upper bits of the CSR address to encode default access privileges. This simplifies error checking in the hardware and provides a larger CSR space, but does constrain the mapping of CSRs into the address space.

Implementations might allow a more-privileged level to trap otherwise permitted CSR accesses by a less-privileged level to allow these accesses to be intercepted. This change should be transparent to the less-privileged software.

Instructions that access a non-existent CSR are reserved. Attempts to access a CSR without appropriate privilege level raise illegal-instruction exceptions or, as described in Section 5.6.1, virtual-instruction exceptions. Attempts to write a read-only register raise illegal-instruction exceptions. A read/write register might also contain some bits that are read-only, in which case writes to the read-only bits are ignored.

Table 3 also indicates the convention to allocate CSR addresses between standard and custom uses. The CSR addresses designated for custom uses will not be redefined by future standard extensions.

Machine-mode standard read-write CSRs 0x7A0‍–‍0x7BF are reserved for use by the debug system. Of these CSRs, 0x7A0‍–‍0x7AF are accessible to machine mode, whereas 0x7B0‍–‍0x7BF are only visible to debug mode. Implementations should raise illegal-instruction exceptions on machine-mode access to the latter set of registers.

note

Effective virtualization requires that as many instructions run natively as possible inside a virtualized environment, while any privileged accesses trap to the virtual machine monitor. [1] CSRs that are read-only at some lower privilege level are shadowed into separate CSR addresses if they are made read-write at a higher privilege level. This avoids trapping permitted lower-privilege accesses while still causing traps on illegal accesses. Currently, the counters are the only shadowed CSRs.

Table 3. Allocation of RISC-V CSR address ranges.

CSR AddressHexUse and Accessibility
[11:10][9:8][7:4]
Unprivileged and User-Level CSRs
0000XXXX0x000‍–‍0x0FFStandard read/write
0100XXXX0x400‍–‍0x4FFStandard read/write
1000XXXX0x800‍–‍0x8FFCustom read/write
11000XXX0xC00‍–‍0xC7FStandard read-only
110010XX0xC80‍–‍0xCBFStandard read-only
110011XX0xCC0‍–‍0xCFFCustom read-only
Supervisor-Level CSRs
0001XXXX0x100‍–‍0x1FFStandard read/write
01010XXX0x500‍–‍0x57FStandard read/write
010110XX0x580‍–‍0x5BFStandard read/write
010111XX0x5C0‍–‍0x5FFCustom read/write
10010XXX0x900‍–‍0x97FStandard read/write
100110XX0x980‍–‍0x9BFStandard read/write
100111XX0x9C0‍–‍0x9FFCustom read/write
11010XXX0xD00‍–‍0xD7FStandard read-only
110110XX0xD80‍–‍0xDBFStandard read-only
110111XX0xDC0‍–‍0xDFFCustom read-only
Hypervisor and VS CSRs
0010XXXX0x200‍–‍0x2FFStandard read/write
01100XXX0x600‍–‍0x67FStandard read/write
011010XX0x680‍–‍0x6BFStandard read/write
011011XX0x6C0‍–‍0x6FFCustom read/write
10100XXX0xA00‍–‍0xA7FStandard read/write
101010XX0xA80‍–‍0xABFStandard read/write
101011XX0xAC0‍–‍0xAFFCustom read/write
11100XXX0xE00‍–‍0xE7FStandard read-only
111010XX0xE80‍–‍0xEBFStandard read-only
111011XX0xEC0‍–‍0xEFFCustom read-only
Machine-Level CSRs
0011XXXX0x300‍–‍0x3FFStandard read/write
01110XXX0x700‍–‍0x77FStandard read/write
0111100X0x780‍–‍0x79FStandard read/write
011110100x7A0‍–‍0x7AFStandard read/write debug CSRs
011110110x7B0‍–‍0x7BFDebug-mode-only CSRs
011111XX0x7C0‍–‍0x7FFCustom read/write
10110XXX0xB00‍–‍0xB7FStandard read/write
101110XX0xB80‍–‍0xBBFStandard read/write
101111XX0xBC0‍–‍0xBFFCustom read/write
11110XXX0xF00‍–‍0xF7FStandard read-only
111110XX0xF80‍–‍0xFBFStandard read-only
111111XX0xFC0‍–‍0xFFFCustom read-only

2.2 CSR Listing​

Table 4‍–‍Table 7 list the CSRs that have currently been allocated CSR addresses. The timers, counters, and floating-point CSRs are standard unprivileged CSRs. The other registers are used by privileged code, as described in the following chapters. Note that not all registers are required on all implementations.

2.2.1 Currently allocated RISC-V unprivileged CSR addresses​

Table 4. Currently allocated RISC-V unprivileged CSR addresses

NumberPrivilegeNameDescription
Unprivileged Floating-Point CSRs
0x001URWfflagsFloating-Point Accrued Exceptions
0x002URWfrmFloating-Point Dynamic Rounding Mode
0x003URWfcsrFloating-Point Control and Status Register (frm + fflags)
Unprivileged Vector CSRs
0x008URWvstartVector start position
0x009URWvxsatFixed-point accrued saturation flag
0x00AURWvxrmFixed-point rounding mode
0x00FURWvcsrVector control and status register
0xC20UROvlVector length
0xC21UROvtypeVector data type register
0xC22UROvlenbVector register length in bytes
Unprivileged Zicfiss Extension CSR
0x011URWsspShadow Stack Pointer
Unprivileged Zkr Extension CSR
0x015URWseedSeed for cryptographic random bit generators
Unprivileged Zcmt Extension CSR
0x017URWjvtTable jump base vector and control register
Unprivileged Counter/Timers
0xC00UROcycleCycle counter for RDCYCLE instruction
0xC01UROtimeTimer for RDTIME instruction
0xC02UROinstretInstructions-retired counter for RDINSTRET instruction
0xC03UROhpmcounter3Performance-monitoring counter
0xC04UROhpmcounter4Performance-monitoring counter
⋮
0xC1FUROhpmcounter31Performance-monitoring counter
0xC80UROcyclehUpper 32 bits of cycle, RV32 only
0xC81UROtimehUpper 32 bits of time, RV32 only
0xC82UROinstrethUpper 32 bits of instret, RV32 only
0xC83UROhpmcounter3hUpper 32 bits of hpmcounter3, RV32 only
0xC84UROhpmcounter4hUpper 32 bits of hpmcounter4, RV32 only
⋮
0xC9FUROhpmcounter31hUpper 32 bits of hpmcounter31, RV32 only

2.2.2 Currently allocated RISC-V supervisor-level CSR addresses​

Table 5. Currently allocated RISC-V supervisor-level CSR addresses

NumberPrivilegeNameDescription
Supervisor Trap Setup
0x100SRWsstatusSupervisor status register
0x104SRWsieSupervisor interrupt-enable register
0x105SRWstvecSupervisor trap handler base address
0x106SRWscounterenSupervisor counter enable
Supervisor Configuration
0x10ASRWsenvcfgSupervisor environment configuration register
Supervisor Counter Setup
0x120SRWscountinhibitSupervisor counter-inhibit register
Supervisor Trap Handling
0x140SRWsscratchSupervisor scratch register
0x141SRWsepcSupervisor exception program counter
0x142SRWscauseSupervisor trap cause
0x143SRWstvalSupervisor trap value
0x144SRWsipSupervisor interrupt pending
0xDA0SROscountovfSupervisor count overflow
Supervisor Indirect
0x150SRWsiselectSupervisor indirect register select
0x151SRWsiregSupervisor indirect register alias
0x152SRWsireg2Supervisor indirect register alias 2
0x153SRWsireg3Supervisor indirect register alias 3
0x155SRWsireg4Supervisor indirect register alias 4
0x156SRWsireg5Supervisor indirect register alias 5
0x157SRWsireg6Supervisor indirect register alias 6
Supervisor Protection and Translation
0x180SRWsatpSupervisor address translation and protection
Supervisor Timer Compare
0x14DSRWstimecmpSupervisor timer compare
0x15DSRWstimecmphUpper 32 bits of stimecmp, RV32 only
Debug/Trace Registers
0x5A8SRWscontextSupervisor-mode context register
Supervisor Resource Management Configuration
0x181SRWsrmcfgSupervisor Resource Management Configuration
Supervisor State Enable Registers
0x10CSRWsstateen0Supervisor State Enable 0 Register
0x10DSRWsstateen1Supervisor State Enable 1 Register
0x10ESRWsstateen2Supervisor State Enable 2 Register
0x10FSRWsstateen3Supervisor State Enable 3 Register
Supervisor Control Transfer Records Configuration
0x14ESRWsctrctlSupervisor Control Transfer Records Control Register
0x14FSRWsctrstatusSupervisor Control Transfer Records Status Register
0x15FSRWsctrdepthSupervisor Control Transfer Records Depth Register

2.2.3 Currently allocated RISC-V hypervisor and VS CSR addresses​

Table 6. Currently allocated RISC-V hypervisor and VS CSR addresses

NumberPrivilegeNameDescription
Hypervisor Trap Setup
0x600HRWhstatusHypervisor status register
0x602HRWhedelegHypervisor exception delegation register
0x603HRWhidelegHypervisor interrupt delegation register
0x604HRWhieHypervisor interrupt-enable register
0x606HRWhcounterenHypervisor counter enable
0x607HRWhgeieHypervisor guest external interrupt-enable register
0x612HRWhedeleghUpper 32 bits of hedeleg, RV32 only
Hypervisor Trap Handling
0x643HRWhtvalHypervisor trap value
0x644HRWhipHypervisor interrupt pending
0x645HRWhvipHypervisor virtual interrupt pending
0x64AHRWhtinstHypervisor trap instruction (transformed)
0xE12HROhgeipHypervisor guest external interrupt pending
Hypervisor Configuration
0x60AHRWhenvcfgHypervisor environment configuration register
0x61AHRWhenvcfghUpper 32 bits of henvcfg, RV32 only
Hypervisor Protection and Translation
0x680HRWhgatpHypervisor guest address translation and protection
Debug/Trace Registers
0x6A8HRWhcontextHypervisor-mode context register
Hypervisor Counter/Timer Virtualization Registers
0x605HRWhtimedeltaDelta for VS/VU-mode timer
0x615HRWhtimedeltahUpper 32 bits of htimedelta, RV32 only
Hypervisor State Enable Registers
0x60CHRWhstateen0Hypervisor State Enable 0 Register
0x60DHRWhstateen1Hypervisor State Enable 1 Register
0x60EHRWhstateen2Hypervisor State Enable 2 Register
0x60FHRWhstateen3Hypervisor State Enable 3 Register
0x61CHRWhstateen0hUpper 32 bits of Hypervisor State Enable 0 Register, RV32 only
0x61DHRWhstateen1hUpper 32 bits of Hypervisor State Enable 1 Register, RV32 only
0x61EHRWhstateen2hUpper 32 bits of Hypervisor State Enable 2 Register, RV32 only
0x61FHRWhstateen3hUpper 32 bits of Hypervisor State Enable 3 Register, RV32 only
Virtual Supervisor Registers
0x200HRWvsstatusVirtual supervisor status register
0x204HRWvsieVirtual supervisor interrupt-enable register
0x205HRWvstvecVirtual supervisor trap handler base address
0x240HRWvsscratchVirtual supervisor scratch register
0x241HRWvsepcVirtual supervisor exception program counter
0x242HRWvscauseVirtual supervisor trap cause
0x243HRWvstvalVirtual supervisor trap value
0x244HRWvsipVirtual supervisor interrupt pending
0x280HRWvsatpVirtual supervisor address translation and protection
Virtual Supervisor Indirect
0x250HRWvsiselectVirtual supervisor indirect register select
0x251HRWvsiregVirtual supervisor indirect register alias
0x252HRWvsireg2Virtual supervisor indirect register alias 2
0x253HRWvsireg3Virtual supervisor indirect register alias 3
0x255HRWvsireg4Virtual supervisor indirect register alias 4
0x256HRWvsireg5Virtual supervisor indirect register alias 5
0x257HRWvsireg6Virtual supervisor indirect register alias 6
Virtual Supervisor Timer Compare
0x24DHRWvstimecmpVirtual supervisor timer compare
0x25DHRWvstimecmphUpper 32 bits of vstimecmp, RV32 only
Virtual Supervisor Control Transfer Records Configuration
0x24EHRWvsctrctlVirtual Supervisor Control Transfer Records Control Register

2.2.4 Currently allocated RISC-V machine-level CSR addresses​

Table 7. Currently allocated RISC-V machine-level CSR addresses

NumberPrivilegeNameDescription
Machine Information Registers
0xF11MROmvendoridVendor ID
0xF12MROmarchidArchitecture ID
0xF13MROmimpidImplementation ID
0xF14MROmhartidHardware thread ID
0xF15MROmconfigptrPointer to configuration data structure
Machine Trap Setup
0x300MRWmstatusMachine status register
0x301MRWmisaISA and extensions
0x302MRWmedelegMachine exception delegation register
0x303MRWmidelegMachine interrupt delegation register
0x304MRWmieMachine interrupt-enable register
0x305MRWmtvecMachine trap-handler base address
0x306MRWmcounterenMachine counter enable
0x310MRWmstatushUpper 32 bits of mstatus, RV32 only
0x312MRWmedeleghUpper 32 bits of medeleg, RV32 only
Machine Trap Handling
0x340MRWmscratchMachine scratch register
0x341MRWmepcMachine exception program counter
0x342MRWmcauseMachine trap cause
0x343MRWmtvalMachine trap value
0x344MRWmipMachine interrupt pending
0x34AMRWmtinstMachine trap instruction (transformed)
0x34BMRWmtval2Machine second trap value
Machine Indirect
0x350MRWmiselectMachine indirect register select
0x351MRWmiregMachine indirect register alias
0x352MRWmireg2Machine indirect register alias 2
0x353MRWmireg3Machine indirect register alias 3
0x355MRWmireg4Machine indirect register alias 4
0x356MRWmireg5Machine indirect register alias 5
0x357MRWmireg6Machine indirect register alias 6
Machine Configuration
0x30AMRWmenvcfgMachine environment configuration register
0x31AMRWmenvcfghUpper 32 bits of menvcfg, RV32 only
0x747MRWmseccfgMachine security configuration register
0x757MRWmseccfghUpper 32 bits of mseccfg, RV32 only
Machine Memory Protection
0x3A0MRWpmpcfg0Physical memory protection configuration
0x3A1MRWpmpcfg1Physical memory protection configuration, RV32 only
0x3A2MRWpmpcfg2Physical memory protection configuration
0x3A3MRWpmpcfg3Physical memory protection configuration, RV32 only
⋮
0x3AEMRWpmpcfg14Physical memory protection configuration
0x3AFMRWpmpcfg15Physical memory protection configuration, RV32 only
0x3B0MRWpmpaddr0Physical memory protection address register
0x3B1MRWpmpaddr1Physical memory protection address register
⋮
0x3EFMRWpmpaddr63Physical memory protection address register
Machine State Enable Registers
0x30CMRWmstateen0Machine State Enable 0 Register
0x30DMRWmstateen1Machine State Enable 1 Register
0x30EMRWmstateen2Machine State Enable 2 Register
0x30FMRWmstateen3Machine State Enable 3 Register
0x31CMRWmstateen0hUpper 32 bits of Machine State Enable 0 Register, RV32 only
0x31DMRWmstateen1hUpper 32 bits of Machine State Enable 1 Register, RV32 only
0x31EMRWmstateen2hUpper 32 bits of Machine State Enable 2 Register, RV32 only
0x31FMRWmstateen3hUpper 32 bits of Machine State Enable 3 Register, RV32 only
Machine Non-Maskable Interrupt Handling
0x740MRWmnscratchResumable NMI scratch register
0x741MRWmnepcResumable NMI program counter
0x742MRWmncauseResumable NMI cause
0x744MRWmnstatusResumable NMI status
Machine Counter/Timers
0xB00MRWmcycleMachine cycle counter
0xB02MRWminstretMachine instructions-retired counter
0xB03MRWmhpmcounter3Machine performance-monitoring counter
0xB04MRWmhpmcounter4Machine performance-monitoring counter
⋮
0xB1FMRWmhpmcounter31Machine performance-monitoring counter
0xB80MRWmcyclehUpper 32 bits of mcycle, RV32 only
0xB82MRWminstrethUpper 32 bits of minstret, RV32 only
0xB83MRWmhpmcounter3hUpper 32 bits of mhpmcounter3, RV32 only
0xB84MRWmhpmcounter4hUpper 32 bits of mhpmcounter4, RV32 only
⋮
0xB9FMRWmhpmcounter31hUpper 32 bits of mhpmcounter31, RV32 only
Machine Counter Setup
0x320MRWmcountinhibitMachine counter-inhibit register
0x321MRWmcyclecfgMachine cycle counter configuration register
0x322MRWminstretcfgMachine instret counter configuration register
0x323MRWmhpmevent3Machine performance-monitoring event selector
0x324MRWmhpmevent4Machine performance-monitoring event selector
⋮
0x33FMRWmhpmevent31Machine performance-monitoring event selector
0x721MRWmcyclecfghUpper 32 bits of mcyclecfg, RV32 only
0x722MRWminstretcfghUpper 32 bits of minstretcfg, RV32 only
0x723MRWmhpmevent3hUpper 32 bits of mhpmevent3, RV32 only
0x724MRWmhpmevent4hUpper 32 bits of mhpmevent4, RV32 only
⋮
0x73FMRWmhpmevent31hUpper 32 bits of mhpmevent31, RV32 only
Machine Control Transfer Records Configuration
0x34EMRWmctrctlMachine Control Transfer Records Control Register
Debug/Trace Registers (shared with Debug Mode)
0x7A0MRWtselectDebug/Trace trigger register select
0x7A1MRWtdata1First Debug/Trace trigger data register
0x7A2MRWtdata2Second Debug/Trace trigger data register
0x7A3MRWtdata3Third Debug/Trace trigger data register
0x7A4MRWtinfoTrigger info register
0x7A5MRWtcontrolTrigger control register
0x7A8MRWmcontextMachine-mode context register
Debug Mode Registers
0x7B0DRWdcsrDebug control and status register
0x7B1DRWdpcDebug program counter
0x7B2DRWdscratch0Debug scratch register 0
0x7B3DRWdscratch1Debug scratch register 1

2.2.5 Currently allocated RISC-V indirect CSR (Smcsrind) mappings​

Table 8. Currently allocated RISC-V indirect CSR (Smcsrind) mappings - M-mode

miselectmiregmireg2mireg3mireg4mireg5mireg6
0x30iprio0nonenonenonenonenone
⋮⋮⋮⋮⋮⋮⋮
0x3Fiprio15nonenonenonenonenone
0x70eideliverynonenonenonenonenone
0x710nonenonenonenonenone
0x72eithresholdnonenonenonenonenone
0x730nonenonenonenonenone
⋮⋮⋮⋮⋮⋮⋮
0x7F0nonenonenonenonenone
0x80eip0nonenonenonenonenone
⋮⋮⋮⋮⋮⋮⋮
0xBFeip63nonenonenonenonenone
0xC0eie0nonenonenonenonenone
⋮⋮⋮⋮⋮⋮⋮
0xFFeie63nonenonenonenonenone

Table 9. Currently allocated RISC-V indirect CSR (Smcsrind/Sscsrind) mappings - S-mode

siselectsiregsireg2sireg3sireg4sireg5sireg6
0x30iprio0nonenonenonenonenone
⋮⋮⋮⋮⋮⋮⋮
0x3Fiprio15nonenonenonenonenone
0x40cyclecyclecfgnonecyclehcyclecfghnone
0x41nonenonenonenonenonenone
0x42instretinstretcfgnoneinstrethinstretcfghnone
0x43hpmcounter3hpmevent3nonehpmcounter3hhpmevent3hnone
⋮⋮⋮⋮⋮⋮⋮
0x5Fhpmcounter31hpmevent31nonehpmcounter31hhpmevent31hnone
0x70eideliverynonenonenonenonenone
0x710nonenonenonenonenone
0x72eithresholdnonenonenonenonenone
0x730nonenonenonenonenone
⋮⋮⋮⋮⋮⋮⋮
0x7F0nonenonenonenonenone
0x80eip0nonenonenonenonenone
⋮⋮⋮⋮⋮⋮⋮
0xBFeip63nonenonenonenonenone
0xC0eie0nonenonenonenonenone
⋮⋮⋮⋮⋮⋮⋮
0xFFeie63nonenonenonenonenone
0x200ctrsource0ctrtarget0ctrdata0000
⋮⋮⋮⋮⋮⋮⋮
0x2FFctrsource255ctrtarget255ctrdata255000

Table 10. Currently allocated RISC-V indirect CSR (Smcsrind/Sscsrind) mappings - VS-mode

vsiselectvsiregvsireg2vsireg3vsireg4vsireg5vsireg6
0x30iprio0nonenonenonenonenone
⋮⋮⋮⋮⋮⋮⋮
0x3Fiprio15nonenonenonenonenone
0x70eideliverynonenonenonenonenone
0x710nonenonenonenonenone
0x72eithresholdnonenonenonenonenone
0x730nonenonenonenonenone
⋮⋮⋮⋮⋮⋮⋮
0x7F0nonenonenonenonenone
0x80eip0nonenonenonenonenone
⋮⋮⋮⋮⋮⋮⋮
0xBFeip63nonenonenonenonenone
0xC0eie0nonenonenonenonenone
⋮⋮⋮⋮⋮⋮⋮
0xFFeie63nonenonenonenonenone
0x200ctrsource0ctrtarget0ctrdata0000
⋮⋮⋮⋮⋮⋮⋮
0x2FFctrsource255ctrtarget255ctrdata255000

2.3 CSR Field Specifications​

The following definitions and abbreviations are used in specifying the behavior of fields within the CSRs.

2.3.1 Reserved Writes Preserve Values, Reads Ignore Values (WPRI)​

Some whole read/write fields are reserved for future use. Software should ignore the values read from these fields, and should preserve the values held in these fields when writing values to other fields of the same register. For forward compatibility, implementations that do not furnish these fields must make them read-only zero. These fields are labeled WPRI in the register descriptions.

note

To simplify the software model, any backward-compatible future definition of previously reserved fields within a CSR must cope with the possibility that a non-atomic read/modify/write sequence is used to update other fields in the CSR. Alternatively, the original CSR definition must specify that subfields can only be updated atomically, which may require a two-instruction clear bit/set bit sequence in general that can be problematic if intermediate values are not legal.

2.3.2 Write/Read Only Legal Values (WLRL)​

Some read/write CSR fields specify behavior for only a subset of possible bit encodings, with other bit encodings reserved. Software should not write anything other than legal values to such a field, and should not assume a read will return a legal value unless the last write was of a legal value, or the register has not been written since another operation (e.g., reset) set the register to a legal value. These fields are labeled WLRL in the register descriptions.

note

Hardware implementations need only implement enough state bits to differentiate between the supported values, but must always return the complete specified bit-encoding of any supported value when read.

Implementations are permitted but not required to raise an illegal-instruction exception if an instruction attempts to write a non-supported value to a WLRL field. Implementations can return arbitrary bit patterns on the read of a WLRL field when the last write was of an illegal value, but the value returned should deterministically depend on the illegal written value and the value of the field prior to the write.

2.3.3 Write Any Values, Reads Legal Values (WARL)​

Some read/write CSR fields are only defined for a subset of bit encodings, but allow any value to be written while guaranteeing to return a legal value whenever read. Assuming that writing the CSR has no other side effects, the range of supported values can be determined by attempting to write a desired setting then reading to see if the value was retained. These fields are labeled WARL in the register descriptions.

Implementations will not raise an exception on writes of unsupported values to a WARL field. Implementations can return any legal value on the read of a WARL field when the last write was of an illegal value, but the legal value returned should deterministically depend on the illegal written value and the architectural state of the hart.

2.4 CSR Field Modulation​

If a write to one CSR changes the set of legal values allowed for a field of a second CSR, then unless specified otherwise, the second CSR’s field immediately gets an UNSPECIFIED value from among its new legal values. This is true even if the field’s value before the write remains legal after the write; the value of the field may be changed in consequence of the write to the controlling CSR.

note

As a special case of this rule, the value written to one CSR may control whether a field of a second CSR is writable (with multiple legal values) or is read-only. When a write to the controlling CSR causes the second CSR’s field to change from previously read-only to now writable, that field immediately gets an UNSPECIFIED but legal value, unless specified otherwise.

Some CSR fields are, when writable, defined as aliases of other CSR fields. Let x be such a CSR field, and let y be the CSR field it aliases when writable. If a write to a controlling CSR causes field x to change from previously read-only to now writable, the new value of x is not UNSPECIFIED but instead immediately reflects the existing value of its alias y, as required.

A change to the value of a CSR for this reason is not a write to the affected CSR and thus does not trigger any side effects specified for that CSR.

2.5 Implicit Reads of CSRs​

Implementations sometimes perform implicit reads of CSRs. (For example, all S-mode instruction fetches implicitly read the satp CSR.) Unless otherwise specified, the value returned by an implicit read of a CSR is the same value that would have been returned by an explicit read of the CSR, using a CSR-access instruction in a sufficient privilege mode.

2.6 CSR Width Modulation​

If the width of a CSR is changed (for example, by changing SXLEN or UXLEN, as described in Section 3.1.6.3), the values of the writable fields and bits of the new-width CSR are, unless specified otherwise, determined from the previous-width CSR as though by this algorithm:

  1. The value of the previous-width CSR is copied to a temporary register of the same width.
  2. For the read-only bits of the previous-width CSR, the bits at the same positions in the temporary register are set to zeros.
  3. The width of the temporary register is changed to the new width. If the new width W is narrower than the previous width, the least-significant W bits of the temporary register are retained and the more-significant bits are discarded. If the new width is wider than the previous width, the temporary register is zero-extended to the wider width.
  4. Each writable field of the new-width CSR takes the value of the bits at the same positions in the temporary register.

Changing the width of a CSR is not a read or write of the CSR and thus does not trigger any side effects.

2.7 Explicit Accesses to CSRs Wider than XLEN​

If a standard CSR is wider than XLEN bits, then an explicit read of the CSR returns the register’s least-significant XLEN bits, and an explicit write to the CSR modifies only the register’s least-significant XLEN bits, leaving the upper bits unchanged.

Some standard CSRs, such as the counter CSRs of extension Zicntr, are always 64-bit, even when XLEN=32 (RV32). For each such 64-bit CSR (for example, counter time), a corresponding 32-bit high-half CSR is usually defined with the same name but with the letter h appended at the end (timeh). The high-half CSR aliases bits 63:32 of its namesake 64-bit CSR, thus providing a way for RV32 software to read and modify the otherwise-unreachable 32 bits.

Standard high-half CSRs are accessible only when the base RISC-V instruction set is RV32 (XLEN=32). For RV64 (when XLEN=64), the addresses of all standard high-half CSRs are reserved, so an attempt to access a high-half CSR typically raises an illegal-instruction exception.