8 `.option`

8.1 rvc/norvc

This option will be deprecated soon after .option arch has been widely implemented on main stream open source toolchains.

Enable/disable the C-extension for the following code region. This option is equivalent to .option arch, +c/.option arch, -c, but widely supported by older toolchain versions.

Alternative style:

.option push
.option arch, +c   # Alternative of .option rvc
.option pop

.option push
.option arch, -c   # Alternative of .option norvc
.option pop

note

.option rvc might set the ELF flag EF_RISCV_RVC in some toolchains. That might cause the linker to compress instructions in code regions where that was not intended.

note

There is a difference between .option rvc/.option norvc and .option arch, +c/.option arch, -c. The latter won’t set EF_RISCV_RVC in the ELF flags.

8.2 arch

Enable and/or disable specific ISA extensions for the following code regions, but without changing the arch attribute and EF_RISCV_RVC in the ELF flags, that means it will not raise the minimal execution environment requirement, so the user should take care to the execution of the code regions around .option push/.option arch/.option pop.

Syntax for .option arch:

.option arch, \<EXTENSIONS-OR-FULLARCH>

EXTENSIONS-OR-FULLARCH := \<EXTENSIONS>
                        | \<FULLARCHSTR>

EXTENSIONS             := \<EXTENSION> ',' \<EXTENSIONS>
                        | \<EXTENSION>

FULLARCHSTR            := \<full-arch-string>

EXTENSION              := \<OP> \<EXTENSION-NAME> \<VERSION>

OP                     := '+'
                        | '-'

VERSION                := [0-9]+ 'p' [0-9]+
                        | [1-9][0-9]*
                        |

EXTENSION-NAME         := Naming rule is defined in RISC-V ISA manual

• Extension version can be omitted, the assembler will use the built-in default version for that extension.
• OP can be enable (+) or disable (-).
• Format of \<full-arch-string\> is the same as -march option.

Example:

.attribute arch, rv64imafdc
# You can only use instructions from the i, m, a, f, d and c extensions.
memcpy_general:
    add     a5,a1,a2
    beq     a1,a5,.L2
    add     a2,a0,a2
    mv      a5,a0
.L3:
    addi    a1,a1,1
    addi    a5,a5,1
    lbu     a4,-1(a1)
    sb      a4,-1(a5)
    bne     a5,a2,.L3
.L2:
    ret

.option push     # Push current options to the stack.
.option arch, +v # Enable vector extension, we can use any instruction in imafdcv extension.
memcpy_vec:
    mv a3, a0
.Lloop:
    vsetvli t0, a2, e8, m8, ta, ma
    vle8.v v0, (a1)
    add a1, a1, t0
    sub a2, a2, t0
    vse8.v v0, (a3)
    add a3, a3, t0
    bnez a2, .Lloop
    ret
.option pop   # Pop current option from the stack, restore the enabled ISA extension status to imafdc.

.option push     # Push current option to the stack.
.option arch, -c # Disable compressed extension, we can't use any instruction in extension.
memcpy_norvc:
    add     a5,a1,a2
    beq     a1,a5,.L2
    add     a2,a0,a2
    mv      a5,a0
.L3:
    addi    a1,a1,1
    addi    a5,a5,1
    lbu     a4,-1(a1)
    sb      a4,-1(a5)
    bne     a5,a2,.L3
.L2:
    ret
.option pop   # Pop current option from the stack, restore the enabled ISA extension status to imafdc.

.option push  # Push current option to the stack.
.option arch, rv64imc # Set arch to rv64imc.
    nop
.option pop   # Pop current option from the stack, restore the enabled ISA extension status to imafdc.

note

A typical use case is with ifunc, e.g. the C library is built with rv64gc, but a few functions like memcpy provide two versions, one built with rv64gc and one built with rv64gcv, and then select between them by ifunc mechanism at run-time. However, we don’t want to change the minimal execution environment requirement to rv64gcv, since the rv64gcv version will be invoked only if the execution environment supports the vector extension, so the minimal execution environment requirement still is rv64gc.

note

.option arch, + will also enable all required extensions, for example, rv32i + .option arch, +v will also enable f, d, zve32x, zve32f, zve64x, zve64f, zve64d, zvl32b, zvl64b and zvl128b extensions.

note

We recommend .option arch, + and .option arch, - are used with .option push/.option pop instead of a .option arch, + / .option arch, - pair, because .option arch, + will enable all required extensions, but .option arch, - only disables the specific extension, so the result might be unexpected, for example: rv32i + .option arch, +v + .option arch, -v will result rv32ifd_zve32x_zve32f_zve64x_zve64f_zve64d_zvl32b_zvl64b_zvl128b not rv32i. Another example is .option arch, rv64ifd + .option arch, -f, which results in rv64ifd, because f will be added back when adding the implied extensions of d.

note

.option arch, +\<ext\>, -\<ext\> is accepted and will result in enabling the extensions that depend on ext, e.g. rv32i + .option arch, +v, -v will result rv32ifd_zve32x_zve32f_zve64x_zve64f_zve64d_zvl32b_zvl64b_zvl128b.

8.3 pic/nopic

Set the code model to PIC (position independent code) or non-PIC. This will affect the expansion of the la pseudoinstruction, refer to listing of standard RISC-V pseudoinstructions.

8.4 relax/norelax

Enable/disable linker relaxation for the following code region.

note

A code region followed by .option relax will emit R_RISCV_RELAX/R_RISCV_ALIGN even if the linker does not support relaxation. The suggested usage is using .option norelax with .option push/.option pop if linker relaxation should be disabled for a code region.

note

Recommended way to disable linker relaxation of specific code region is use .option push, .option norelax and .option pop, that prevent enabled linker relaxation accidentally if user already disable linker relaxation.

8.5 push/pop

Push/pop current options to/from the options stack.